Method for forming a bump, semiconductor device and method of fabricating same, semiconductor chip, circuit board, and electronic instrument

ABSTRACT

A method for forming a bump includes the steps of forming a resist layer so that a through-hole formed therein is located on a pad; and forming a metal layer to be electrically connected to the pad conforming to the shape of the through-hole. The metal layer is formed so as to have a shape in which is formed a region for receiving a soldering or brazing material.

[0001] Japanese Patent Application No. 2000-267076, filed Sep. 4, 2000,is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

[0002] The present invention relates to a method for forming a bump, asemiconductor device and a method of fabricating the same, asemiconductor chip, a circuit board, and an electronic instrument.

BACKGROUND

[0003] A method is known in the art in which metal bumps are formed onpads of a semiconductor chip by applying electroless plating or thelike. The semiconductor chip is electrically connected to aninterconnect pattern (leads) on a substrate by allowing solder appliedto the metal bumps to melt, for example. According to this method, thepads can be connected to the leads by melting the solder, differing fromthe case of connecting the pads to the leads by applying heat andpressure to the leads, thereby decreasing the amount of pressure appliedto the surface of the semiconductor chip. This allows the pads to bedisposed not only in the end sections of the semiconductor chip but alsoin a device formation region, whereby a larger number of pads can bedisposed at a coarser pitch. Moreover, use of solder ensures that asemiconductor device can be fabricated at low cost in comparison withthe case of forming gold bumps.

[0004] However, according to this configuration, solder applied to eachpad may flow onto the adjacent pads upon melting when connecting thepads to the interconnect pattern, thereby causing a short circuit tooccur between the pads. This problem cannot be solved by merelydecreasing the amount of solder applied to each pad.

SUMMARY

[0005] A method for forming a bump according to the first aspect of thepresent invention comprises the steps of:

[0006] forming a resist layer so that a through-hole formed therein islocated on a pad; and

[0007] forming a metal layer to be electrically connected to the padconforming to the shape of the through-hole,

[0008] wherein the metal layer is formed so as to have a shape in whichis formed a region for receiving a soldering or brazing material.

[0009] A method of fabricating a semiconductor device according to thesecond aspect of the present invention comprises the steps of:

[0010] bonding a plurality of metal layers to a plurality of leadsthrough a soldering or brazing material, each of the metal layers formedon each of a plurality of pads of a semiconductor chip, each of themetal layers having a shape in which is formed a region for receivingthe soldering or brazing material,

[0011] wherein the soldering or brazing material, when melted, isallowed to flow into the region of each of the metal layers forreceiving the soldering or brazing material so as not to spread onto anadjacent pad of the plurality of pads.

[0012] A semiconductor device according to the third aspect of thepresent invention is fabricated by the above method of fabricating asemiconductor device.

[0013] A semiconductor chip according to the fourth aspect of thepresent invention comprises a plurality of pads, and a metal layerdisposed on each of the pads which is formed to have a shape in which isformed a region for receiving a soldering or brazing material.

[0014] A semiconductor device according to the fifth aspect of thepresent invention comprises:

[0015] a semiconductor chip having a plurality of pads;

[0016] a metal layer disposed on each of the pads, the metal layerformed to have a shape in which is formed a region for receiving asoldering or brazing material; and

[0017] a plurality of leads,

[0018] wherein the metal layer is bonded to one of the leads through thesoldering or brazing material, and part of the soldering or brazingmaterial is put in the region for receiving the soldering or brazingmaterial.

[0019] According to the sixth aspect of the present invention, there isprovided a circuit board on which the above semiconductor device ismounted.

[0020] An electronic instrument according to the seventh aspect of thepresent invention comprises the above semiconductor device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a view showing a method for forming bumps according to afirst embodiment to which the present invention is applied.

[0022]FIG. 2 is a view showing the method for forming bumps according tothe first embodiment to which the present invention is applied.

[0023]FIGS. 3A to 3C are views showing the method for forming bumpsaccording to the first embodiment to which the present invention isapplied.

[0024]FIGS. 4A to 4C are views showing the method for forming bumpsaccording to the first embodiment to which the present invention isapplied.

[0025]FIG. 5 is a view showing the method for forming bumps according tothe first embodiment to which the present invention is applied.

[0026]FIGS. 6A to 6C are views showing the method for forming bumpsaccording to a modification example of the first embodiment to which thepresent invention is applied.

[0027]FIG. 7 is a view showing a semiconductor device and a method offabricating the semiconductor device according to the first embodimentto which the present invention is applied.

[0028]FIG. 8 is a view showing a method for forming bumps according to asecond embodiment to which the present invention is applied.

[0029]FIGS. 9A to 9C are views showing the method for forming bumpsaccording to the second embodiment to which the present invention isapplied.

[0030]FIG. 10 is a view showing the method for forming bumps accordingto the second embodiment to which the present invention is applied.

[0031]FIG. 11 is a view showing a method for forming bumps according amodification example of the second embodiment to which the presentinvention is applied.

[0032]FIGS. 12A and 12B are views showing a method for forming bumpsaccording to a third embodiment to which the present invention isapplied.

[0033]FIG. 13 is a view showing a circuit board equipped with asemiconductor device according to an embodiment to which the presentinvention is applied.

[0034]FIG. 14 is a view showing an electronic instrument equipped with asemiconductor device according to an embodiment to which the presentinvention is applied.

[0035]FIG. 15 is a view showing an electronic instrument equipped with asemiconductor device according to an embodiment to which the presentinvention is applied.

DETAILED DESCRIPTION

[0036] The embodiment of the present invention has been achieved tosolve the above conventional problem. An object of the embodiment of thepresent invention is to provide a method for forming a bump capable ofdealing with a fine pitch with high reliability, a semiconductor deviceand a method of fabricating the same, a semiconductor chip, a circuitboard, and an electronic instrument.

[0037] (1) A method for forming a bump according to one embodiment ofthe present invention comprises the steps of:

[0038] forming a resist layer so that a through-hole formed therein islocated on a pad; and

[0039] forming a metal layer to be electrically connected to the padconforming to the shape of the through-hole,

[0040] wherein the metal layer is formed so as to have a shape in whichis formed a region for receiving a soldering or brazing material.

[0041] According to this embodiment of the present invention, the metallayers are formed into a specific shape conforming to the shape of thethrough-holes. The metal layers have a region for receiving the brazingmaterial. This allows the brazing material to flow into the above regionof the metal layers, thereby preventing the brazing material fromspreading outside the metal layers. Specifically, the brazing materialmelted on the metal layers can be prevented from flowing onto theadjacent pads, for example. Therefore, occurrence of a short circuitbetween the pads can be prevented, whereby the yield in the fabricationcan be increased.

[0042] (2) In this method for forming a bump,

[0043] the resist layer may be formed so as to have a projection on theinner side of the through-hole.

[0044] This enables the formation of depressions in the sides of themetal layers. This allows the brazing material to flow into thedepressions of the metal layers, thereby preventing the brazing materialfrom spreading outside the metal layers.

[0045] (3) In this method for forming a bump,

[0046] the resist layer may be formed so that part of the resist layerremains at the center of the through-holes.

[0047] This enables the formation of the region for receiving thebrazing material at the center of the metal layers. This allows thebrazing material to flow into the region at the center of the metallayers, thereby preventing the brazing material from spreading outsidethe metal layers.

[0048] (4) In this method for forming a bump,

[0049] a plurality of the through-holes may be formed in the resistlayer so that at least a part of each of the through-holes is superposedon the pad, and

[0050] a plurality of the metal layers may be formed, each of theplurality of the metal layers conforming to each of the through-holes toform the region for receiving the soldering or brazing material betweenthe adjacent metal layers of the plurality of the metal layers on thepad.

[0051] This prevents the brazing material from spreading outside themetal layers by allowing the brazing material to flow into the regionformed between the adjacent metal layers on each pad.

[0052] (5) In this method for forming a bump,

[0053] the metal layer may comprise first and second metal

[0054] wherein the first metal layer may be formed in a state in whichthe resist layer is formed, and the second metal layer may be formed onthe first metal layer.

[0055] In the case where a material to which the brazing materialreadily adheres in comparison with the first metal layers is used as thematerial for the second metal layers, the brazing material can beapplied only to the upper surface of the metal layers. Specifically,this prevents the brazing material from spreading outside the metallayers more reliably.

[0056] (6) In this method for forming a bump,

[0057] the metal layer may comprise first and second metal layers,

[0058] wherein the first metal layer may be formed in a state in whichthe resist layer is formed, and

[0059] after removing the resist layer, the second metal layer may beformed so as to cover a surface of the first metal layer.

[0060] This prevents the surface of the first metal layer from beingoxidized.

[0061] (7) In this method for forming a bump,

[0062] the pad may be covered with an insulating film,

[0063] the resist layer may be formed on the insulating film,

[0064] an opening for exposing at least part of the pad may be formed inthe insulating film after forming the through-hole in the resist layer,and

[0065] the first metal layer may be formed on the pad in a state inwhich the resist layer is formed.

[0066] Since the openings are formed in the insulating film and thefirst metal layers to be electrically connected to the pads are formedusing the through-holes in the same resist layer, the bumps can beformed by simplified steps.

[0067] (8) In this method for forming a bump,

[0068] the first and second metal layers may be formed by electrolessplating.

[0069] (9) In this method for forming a bump,

[0070] the first metal layer may be formed of a material containingnickel.

[0071] (10) In this method for forming a bump,

[0072] the second metal layers may be formed using a material containinggold.

[0073] (11) A method of fabricating a semiconductor device according toanother embodiment of the present invention comprises the steps of:

[0074] bonding a plurality of metal layers to a plurality of leadsthrough a soldering or brazing material, each of the metal layers formedon each of a plurality of pads of a semiconductor chip, each of themetal layers having a shape in which is formed a region for receivingthe soldering or brazing material,

[0075] wherein the soldering or brazing material, when melted, isallowed to flow into the region of each of the metal layers forreceiving the soldering or brazing material so as not to spread onto anadjacent pad of the plurality of pads.

[0076] According to this embodiment of the present invention, thebrazing material applied between the metal layers and the leads isallowed to flow into the region of the metal layer, thereby preventingthe brazing material from spreading outside the metal layers.Specifically, the brazing materials melted on the metal layers can beprevented from flowing onto the adjacent pads. Therefore, occurrence ofa short circuit between the pads can be prevented, whereby the yield inthe fabrication can be increased.

[0077] (12) In this method of fabricating a semiconductor device,

[0078] at least one depression may be formed in a side of one of themetal layers, and

[0079] the soldering or brazing material may be allowed to flow into thedepression.

[0080] This prevents the brazing material from spreading outside themetal layers by allowing the brazing material to flow into thedepression of the metal layers.

[0081] (13) In this method of fabricating a semiconductor device,

[0082] one of the metal layer may be formed so that a depression whichis provided in the direction of the height of the metal layers is formedat the center, and

[0083] the soldering or brazing material may be allowed to flow into thedepression.

[0084] This prevents the brazing material from spreading outside themetal layers by allowing the brazing material to flow into thedepression which is provided in the direction of the height of the metallayers.

[0085] (14) In this method of fabricating a semiconductor device,

[0086] two or more metal layers of the plurality of metal layers may beformed so as to be connected to one of the pads, and

[0087] the soldering or brazing material may be allowed to flow into aregion formed between the adjacent metal layers of the plurality ofmetal layers on one of the pads.

[0088] This prevents the brazing material from spreading outside themetal layers by allowing the brazing material to flow into the regionformed between the adjacent metal layers on each pad.

[0089] (15) A semiconductor device according to an embodiment of thepresent invention is fabricated by the above method of fabricating asemiconductor device.

[0090] (16) A semiconductor chip according to further embodiment of thepresent invention comprises a plurality of pads, and a metal layerdisposed on each of the pads which is formed to have a shape in which isformed a region for receiving a soldering or brazing material.

[0091] (17) In this semiconductor chip,

[0092] at least one depression may be formed in a side of the metallayer.

[0093] (18) In this semiconductor chip,

[0094] a depression which is provided in the direction of the height ofthe metal layers may be formed at the center of the metal layers.

[0095] (19) In this semiconductor chip, two or more the metal layers maybe formed on one of the pads.

[0096] (20) A semiconductor device according to still another embodimentof the present invention comprises:

[0097] a semiconductor chip having a plurality of pads;

[0098] a metal layer disposed on each of the pads, the metal layerformed to have a shape in which is formed a region for receiving asoldering or brazing material; and

[0099] a plurality of leads,

[0100] wherein the metal layer is bonded to one of the leads through thesoldering or brazing material, and part of the soldering or brazingmaterial is put in the region for receiving the soldering or brazingmaterial.

[0101] According to this embodiment of the present invention, thebrazing material can be prevented from spreading outside the metal layerby allowing part of the brazing material to flow into the region of themetal layers. Specifically, the brazing material melted on the metallayers can be prevented from flowing onto the adjacent pads. Therefore,a highly reliable semiconductor device can be provided by preventingoccurrence of a short circuit between the pads.

[0102] (21) In this semiconductor device,

[0103] at least one depression may be formed in a side of the metallayer, and

[0104] the soldering or brazing material may be put in the depression.

[0105] (22) In this semiconductor device,

[0106] a depression which is provided in the direction of the height ofthe metal layer may be formed at the center of the metal layer, and

[0107] the soldering or brazing material may be put in the depression.

[0108] (23) In this semiconductor device,

[0109] two or more the metal layers may be formed on one of the pads,and

[0110] the soldering or brazing material may be put in a region formedbetween adjacent metal layers of the two or more the metal layers on oneof the pads.

[0111] (24) According to still another embodiment of the presentinvention, there is provided a circuit board on which the abovesemiconductor device is mounted.

[0112] (25) An electronic instrument according to yet another embodimentof the present invention comprises the above semiconductor device.

[0113] Preferred embodiments of the present invention are describedbelow with reference to the drawings. However, the present invention isnot limited to the following embodiments.

[0114] (First Embodiment)

[0115] FIGS. 1 to 6C are views showing a method for forming bumpsaccording to a first embodiment to which the present invention isapplied. The present embodiment illustrates an example in which bumpsare formed on a semiconductor chip. However, the method for formingbumps according to the present invention is not limited thereto. Themethod may be applied for forming bumps on leads. The leads may be aninterconnect pattern formed on a substrate. In this case, lands of theinterconnect pattern correspond to pads. The present invention may beapplied when forming bumps on pads formed on a semiconductor wafer.

[0116] In the present embodiment, a semiconductor chip 10 shown in FIG.1 is provided. The semiconductor chip 10 is generally formed in theshape of a rectangular parallelepiped (including cube). Thesemiconductor chip 10 may be formed in the shape of a sphere, forexample. The thickness of the semiconductor chip 10 is not limited. Thesemiconductor chip 10 ground into a thin piece may be used.

[0117] The semiconductor chip 10 includes a plurality of pads 12. Thepads 12 become electrodes for an integrated circuit formed inside thesemiconductor chip 10. The pads 12 are generally formed on the side ofthe semiconductor chip 10 on which the integrated circuit is formed. Inthis case, the pads 12 may be formed either outside or inside the regionin which the integrated circuit is formed. The pads 12 are formed in oneor more of columns at the ends or center of the semiconductor chip 10.The pads 12 may be arranged in a matrix of a plurality of rows andcolumns on the surface of the semiconductor chip 10.

[0118] The planar shape of the pads 12 may be either rectangular orcircular. The pads 12 are generally formed using a material containingaluminum. The pads 12 may be formed using a material containing copperor the like.

[0119] An insulating film 14 is formed on the surface of thesemiconductor chip 10 on which the pads 12 are formed. In the presentembodiment, the insulating film 14 is formed so as to cover each pad 12,as shown in FIG. 1. Specifically, the semiconductor chip 10 in whicheach pad 12 is not exposed through the insulating film 14 may be used.In the present embodiment, bumps are formed on the pads 12 using aresist layer formed to allow each pad 12 to be exposed through theinsulating film 14.

[0120] The insulating film 14 is formed of either a single layer or aplurality of layers. The thickness of the insulating film 14 is notlimited. The insulating film 14 may be referred to as a passivationfilm. The insulating film 14 is formed using SiO₂, SiN, a polyimideresin, or the like.

[0121] A method of fabricating a semiconductor device according to thepresent embodiment includes the following steps using the semiconductorchip 10. The following description is also applicable to semiconductorwafer processing.

[0122] A resist layer 20 is formed on the semiconductor chip 10, asshown in FIGS. 2 and 3A. FIG. 2 is a plan view and FIG. 3 is across-sectional view showing the semiconductor chip 10. The resist layer20 is formed on the surface of the semiconductor chip 10 on which thepads 12 are formed, specifically, on the insulating film 14. Thethickness of the resist layer 20 may be appropriately determineddepending on the height of bumps which are formed later. The resistlayer 20 may be formed to a thickness of about 20 μm, for example.

[0123] The resist layer 20 has through-holes 22 formed therein above thepads 12, specifically, on the insulating film 14. Specifically, thethrough-holes 22 are formed so that at least part (part or all) of thethrough-holes 22 is superposed on the pads 12. Allowing part of thethrough-holes 22 to be superposed on the pads 12 enables the bumpsformed in the through-holes 22 to be electrically connected to the pads12.

[0124] In the present embodiment, the through-holes 22 are formed sothat projections are formed on the inner side of the through-holes 22,as shown in FIG. 2. In other words, a plurality of projections is formedon the wall surface of the resist layer 20 in contact with thethrough-holes 22. One or a plurality of projecting sections 24 is formedon the resist layer 20. The planar shape of the through-holes 22 may besimilar to the shape of the pads 12, wherein part of the resist layer 20projects to each side toward the inside of the through-holes 22. Theplanar shape of the through-holes 22 may be circular, wherein part ofthe resist layer 20 projects toward the inside of the through-holes 22.Depressions 36 (see FIG. 5) can be formed in the side of the bumps byforming the projecting sections 24 of the resist layer 20. Thethrough-holes 22 may be formed through the resist layer 20 in the sameplanar shape in the direction of the thickness of the resist layer 20.

[0125] Photolithographic technology may be applied as a method forforming the resist layer 20. Specifically, the photosensitive resistlayer 20 may be exposed to energy through a mask (not shown) andsubjected to development, thereby forming the through-holes 22. Thethrough-holes 22 can be formed into a specific shape by forming a maskso that the resist layer 20 projects toward the inside of thethrough-holes 22. The resist layer 20 may be either a positive resist ora negative resist.

[0126] The through-holes 22 may be formed into a specific shape byetching the non-photosensitive resist layer 20. The resist layer 20 maybe formed by applying screen printing or an ink-jet method insofar asthe through-holes 22 are formed into a specific shape.

[0127] The through-holes 22 may be formed so as not to cross thecircumference of the pads 12, as shown in FIG. 2. This enables the bumpsto be formed without causing a short circuit to occur between adjacentpads 12 even if the pitch between each pad 12 is extremely fine. Thethrough-holes 22 may be formed so as to be larger than the circumferenceof the pads 12. The through-holes 22 may be formed so that part of thecircumference thereof intersects the circumference of the pads 12.

[0128] Part of the insulating film 14 is removed through thethrough-holes 22 formed in the resist layer 20, as shown in FIG. 3B.Specifically, openings 26 for exposing at least part (part or all) ofthe pads 12 are formed by removing the insulating film 14 in the areainside the through-holes 22. The openings 26 may be formed by etching.The etching technique may be either a chemical or physical technique, ora combination of these techniques. Etching characteristics may be eitherisotropic or an isotropic. In the case where isotropic etching isapplied, the openings 26 in the insulating film 14 may be formed outsidethe circumference of the through-holes 22. The openings 26 in theinsulating film 14 may be formed inside the circumference of the pads12. The openings 26 in the insulating film 14 may be formed outside thecircumference of the pads 12. The size of the exposed area of the pads12 by the openings 26 is not limited. For example, the exposed area maybe in the shape of a square having a side length of about 20 μm.

[0129] First metal layers 30 are formed conforming to the shape of thethrough-holes 22, as shown in FIG. 3C. Specifically, the first metallayers 30 are formed along the inner side of the through-holes 22. Thethrough-holes 22 may be completely filled with the first metal layers 30so that the surfaces of the first metal layers 30 and the resist layer20 are level. The first metal layers 30 may be either higher than orlower than the surface of the resist layer 20. The first metal layers 30can be formed into a specific shape by forming the first metal layers 30along the inner sides of the through-holes 22.

[0130] Since the through-holes 22 link with the openings 26 in theinsulating film 14, the bumps to be electrically connected to the pads12 can be formed by forming the first metal layers 30 in thethrough-holes 22. The first metal layers 30 may be formed of either asingle layer as shown in FIG. 3C or a plurality of layers. The firstmetal layers 30 may be formed using a material containing nickel. Use ofnickel layers as the first metal layers 30 enables the bumps to beformed at low cost in a comparatively short period of time. The firstmetal layers 30 may be formed using a material containing gold.

[0131] The first metal layers 30 may be formed by electroless plating. Amethod for forming the nickel layers (first metal layers 30) on the pads12 containing aluminum is described below.

[0132] The surface (aluminum) of the pads 12 may be replaced by zincusing a zincate treatment. Specifically, aluminum is replaced by zinc byapplying an alkaline zinc solution onto the surface of each pad 12. Inthis case, the semiconductor chip 10 may be dipped into an alkaline zincsolution. It is preferable to heat the resist layer 20 in advance forthis treatment at a temperature of about 100-200° C. for severalminutes. This provides the resist layer 20 with an increased resistanceto a strong alkaline solution. Specifically, the resist layer 20 becomesscarcely soluble. The resist layer 20 may be irradiated with ultravioletrays in order to prevent heat deformation of the resist layer 20. It ispreferable to use ultraviolet rays with a dominant wavelength of 254 nm.The dose may be appropriately adjusted depending on the thickness of theresist layer 20. It is advantageous to irradiate the resist layer 20with ultraviolet rays while allowing a solvent included in the resistlayer 20 to volatile under reduced pressure. It is also advantageous toheat the resist layer 20 and the like at a temperature of about 100-200°C. during irradiation with ultraviolet rays.

[0133] It is preferable to dissolve residual insulating films 14remaining on the semiconductor chip 10 before dipping the pads 12 intoan alkaline zinc solution. The residual insulating films 14 may bedissolved by dipping the semiconductor chip 10 into a weak hydrogenfluoride solution. After dissolving the residual insulating films 14, itis preferable to remove oxide films formed in the exposed area of thepads 12 by dipping the pads 12 into an alkaline solution. This enablesthe surface of the pads 12 to be reliably exposed, whereby aluminum onthe surface of the pads 12 can be replaced by zinc.

[0134] Zinc may be deposited on the surface of the pads 12 by dippingthe pads 12 into an alkaline zinc solution, dissolving zinc by whichaluminum is replaced using nitric acid, and further dipping the pads 12into an alkaline zinc solution. This enables zinc to be reliablydeposited on the surface of the pads 12.

[0135] The pads 12 are dipped into an electroless nickel solution,thereby forming the nickel layers (first metal layers 30) in thethrough-holes 22. In this case, the solution maybe heated. For example,an electroless nickel solution (4.5 pH) may be heated at a temperatureof about 90° C. The semiconductor chip 10 is dipped into this solutionfor about 45 minutes, thereby forming the nickel layers (first metallayers 30) with a thickness of about 20 μm. The thickness of the firstmetal layers 30 may be either smaller than or greater than the height ofthe through-holes 22. The thickness of the first metal layers 30 may beappropriately determined by a period of time for dipping the pads 12into the solution or the like.

[0136] Other metal layers may be interposed between the pads 12 and thefirst metal layers 30. For example, in the case of forming the firstmetal layers 30 on the pads 12 by the zincate treatment, part of thezinc layers remaining on the aluminum (pads 12) may be interposedbetween the first metal layers 30 and the pads 12.

[0137] Differing from the above example, a solution containing areducing agent such as palladium may be applied to the pads 12 and anelectroless nickel solution may be applied thereafter, thereby formingthe nickel layers (first metal layers 30) with palladium as nuclei.

[0138] In the above steps, the first metal layers 30 are formed in thethrough-holes 22 while allowing the resist layer formed to expose eachpad 12 to remain. Specifically, the openings 26 are formed in theinsulating film 14 and the first metal layers 30 connected to the pads12 are formed using the same resist layer 20, whereby the bumps can beformed by simplified steps.

[0139] After forming the first metal layers 30, the resist layer 20 isremoved, as shown in FIG. 4A. The first metal layers 30 are formedconforming to the shape of the through-holes 22 by the above steps.

[0140] Second metal layers 32 may be optionally formed on the surface ofthe first metal layers 30, as shown in FIG. 4B. The second metal layers32 may be formed of a single layer as shown in FIG. 4B or a plurality oflayers. It is preferable to form the second metal layers 32 conformingto the shape of the first metal layers 30. Specifically, it ispreferable to form thin second metal layers 32 so that the depressionsin the first metal layers 30 are not filled with the second metal layers32. The second metal layers 32 may be formed so as to cover the surfaceof the first metal layers 30. This prevents the surface of the firstmetal layers 30 from being oxidized. It is preferable to form at leastthe surface of the second metal layers 32 using a material containinggold.

[0141] The second metal layers 32 may be formed by electroless plating.For example, gold layers (second metal layers 32) may be formed on thesurface of the nickel layers (first metal layers 30) by dipping thesemiconductor chip 10 into an electroless gold plating solution. Thethickness of the gold layers (second metal layers 32) is not limitedinsofar as the gold layers can be formed on the surface of the firstmetal layers 30. For example, the gold layers (second metal layers 32)may be formed to a thickness of about 0.15 μm.

[0142] In the case of forming the first metal layers 30 or second metallayers 32 by electroless plating by dipping the semiconductor chip 10into a desired solution, it is preferable to cover the side and the backface of the semiconductor chip 10 with a protective film in advance. Aresist layer may be used as the protective film. In this case, theresist layer may be a non-photosensitive resist. The resist layer may beformed to a thickness of about 2 μm on the side and the back face of thesemiconductor chip 10. Potential changes in each pad 12 of thesemiconductor chip 10 caused by dipping the semiconductor chip 10 intothe solution can be prevented by thus forming a protective film.Specifically, treatment for each pad 12 such as deposition of a metal byelectroless plating can be more uniform.

[0143] It is preferable to eliminate light when dipping thesemiconductor chip 10 into a desired solution. This prevents theoccurrence of potential changes in each pad 12 of the semiconductor chip10.

[0144] Bumps 34 including the first and second metal layers 30 and 32can be formed in this manner, as shown in FIG. 4C. Brazing materials 40may be further applied to the second metal layers 32, as shown in FIG.4C. The soldering or brazing materials 40 are applied to each secondmetal layer 32. The soldering or brazing materials 40 may be solder. Forexample, solder balls (soldering or brazing materials 40) may be formedon the bumps 34 by dipping the upper surface of the bumps 34 (part ofthe second metal layers 32) into a solder bath. Since solder readilyadheres to the gold layers (second metal layers 32), solder (solderingor brazing materials 40) can be easily applied to the bumps 34. Soldermay be formed using a material containing tin and silver, for example.The height of the solder balls (soldering or brazing materials 40) isnot limited. For example, the height of the solder balls may be about 15μm. In the case of applying the soldering or brazing materials 40 to thesemiconductor chip 10, the first and second metal layers 30 and 32 andthe soldering or brazing material 40 may be collectively referred to asa bump.

[0145]FIG. 5 is a lateral cross-sectional view showing the bumps 34(first and second metal layers 30 and 32) parallel to the plan view ofthe semiconductor chip 10. At least one depression 36 (region forreceiving soldering or brazing materials 40) is formed on the side ofthe bumps 34, as shown in FIG. 5. Specifically, part of the first metallayers 30 is made concave by the projecting sections 24 (see FIG. 2) ofthe resist layer 20 by forming the first metal layers 30 conforming tothe shape of the through-holes 22. The second metal layers 32 are formedconforming to the shape of the first metal layers 30. The depressions ofthe first metal layers 30 are formed as the depressions 36 of the bumps34.

[0146] This allows the soldering or brazing materials 40 to flow intothe depressions 36 of the bumps 34 when allowing the soldering orbrazing materials 40 to melt on the bumps 34. Since the depressions 36are formed toward the inside of the bumps 34, the soldering or brazingmaterials 40 can be absorbed into the inside the bumps 34. This preventspart of the soldering or brazing materials 40 flowing out from the bumps34 upon melting from spreading in the direction parallel to the surfaceof the semiconductor chip 10 (lateral direction), whereby the solderingor brazing materials 40 can be absorbed in the direction of the heightof the bumps 34 (vertical direction) Therefore, even if each pad 12 isformed at a fine pitch, the soldering or brazing materials 40 can beused without allowing the soldering or brazing materials 40 to flow ontothe adjacent pads 12, specifically, without causing a short circuit tooccur.

[0147] The depressions 36 of the bumps 34 may be formed so that the peakof a triangle faces the center, as shown in FIG. 5. The depressions 36of the bumps 34 may be formed in the shape of a quadrangle or asemicircle toward the center of the bumps 34. The depressions 36 may beformed in other shapes. In the case where one side of the bumps 34 isabout 20 μm and the pitch between each pad 12 is about 40 μm in a planview of the semiconductor chip 10, the depressions 36 of the bumps 34may be formed at a depth of about 5 μm from the end sections toward thecenter. This enables the soldering or brazing materials 40 to beabsorbed effectively.

[0148] Differing from the example shown in FIG. 5, the depressions 36 ofthe bumps 34 may be formed only on the sides of the bumps 34 facing theadjacent pads 12 (bumps 34). For example, in the case where the pads 12are formed in one row in the end sections of the semiconductor chip 10,the depressions 36 may be formed only on the sides of the bumps 34 oneach pad 12 facing both adjacent pads 12. This prevents the soldering orbrazing materials 40 from spreading in the directions of the adjacentpads 12, thereby preventing occurrence of a short circuit between thepads 12. In the case where each pad 12 is formed in a matrix, forexample, the depressions 36 are preferably formed on all sides of thebumps 34.

[0149]FIGS. 6A to 6C are views showing a method for forming bumpsaccording to a modification example of the present embodiment. Thismodification example differs from the above-described embodiment as tothe structure of second metal layers 33.

[0150] The second metal layers 33 are formed in the through-holes 22formed in the resist layer 20, as shown in FIG. 6A. Specifically, thesecond metal layers 33 are formed on the upper surface of the firstmetal layers 30 without removing the resist layer 20. At least thesurface of the second metal layers 33 may be formed using a materialcontaining gold. Gold layers (second metal layers 33) may be formed to athickness of about 0.1 μm. The second metal layers 33 may be formed byelectroless plating. Other formation method and structure of the secondmetal layers 33 are the same as described above.

[0151] After forming the second metal layers 33, the resist layer 20 isremoved, as shown in FIG. 6B. The first and second metal layers 30 and33 are formed conforming to the shape of the through-holes 22.

[0152] Bumps 35 in which the second metal layers 33 are formed on theupper surface of the first metal layers 30 are formed in this manner, asshown in FIG. 6C. In other words, the bumps 35 include the gold layers(second metal layers 33) only on the upper surface thereof, for example.This enables solder balls (soldering or brazing materials 40) to beformed only on the upper surface of the bumps 35 by dipping the bumps 35into a solder bath, for example. Specifically, allowing no gold layer(second metal layer 33) to be formed on the side of the bumps 35 morereliably prevents the solder (soldering or brazing material 40) fromspreading in the lateral direction from the side of the bumps 35 uponmelting.

[0153] In the above example, the bumps 34 are formed using the sameresist layer 20 used to allow the insulating film 14 to expose each pad12. Differing from this example, the bumps 34 may be formed by forminganother resist layer after removing the resist layer. In this case,through-holes in the resist layer for forming openings in the insulatingfilm 14 which is formed first may be in the shape of either a square ora circle having no depressions. The bumps 34 having the depressions 36can be formed by forming a resist layer for forming the metal layers(first metal layer 30, for example), which is formed later, so as tohave the through-holes 22 formed therein.

[0154] According to the method for forming bumps of the presentembodiment, the metal layers (bumps 34) are formed into a specific shapeconforming to the shape of the through-holes 22. The metal layers (bumps34) have regions for receiving the soldering or brazing materials 40.This prevents the soldering or brazing materials 40 from spreadingoutside the metal layers (bumps 34) by allowing the soldering or brazingmaterials 40 to flow into these regions of the metal layers (bumps 34).Specifically, the soldering or brazing materials 40 melted on the metallayers (bumps 34) can be prevented from flowing onto the adjacent pads12, for example. Therefore, the yield in the fabrication can beincreased by preventing occurrence of a short circuit between the pads12.

[0155] In the case where the pads 12 are formed using a materialcontaining copper, when forming nickel layers (first metal layers 30) oncopper, for example, a solution containing a reducing agent such aspalladium is applied to the pads 12 and an electroless nickel solutionis then applied, thereby forming the nickel layers (first metal layers30) with palladium as nuclei.

[0156] The above metals and solutions are only examples. The presentembodiment is not limited thereto. For example, copper may be used as ametal used for electroless plating.

[0157] A method of fabricating a semiconductor device according to thepresent embodiment includes a step of bonding the metal layers (firstand second metal layers 30 and 32) connected to a plurality of pads 12of the semiconductor chip 10 to a plurality of leads (interconnectpattern 52) through the soldering or brazing materials 40, as shown inFIG. 7. The metal layers have regions for receiving the soldering orbrazing materials 40. The metal layers may be the bumps 34 (first andsecond metal layers 30 and 32) in which the depressions 36 are formed bythe above formation method. Specifically, the regions for receiving thesoldering or brazing materials 40 correspond to the depressions 36 ofthe bumps 34.

[0158] Each bump 34 is electrically connected to one of the leadsthrough the soldering or brazing material 40. The leads may be theinterconnect pattern 52 formed on a substrate 50. In this case, thesemiconductor chip 10 may be bonded face down to the substrate 50. Thebumps 34 may be bonded to the lands of the interconnect pattern 52.

[0159] The melting soldering or brazing materials 40 are absorbed intothe depressions 36 of the bumps 34 when bonding the bumps 34 to theinterconnect pattern 52. Specifically, the soldering or brazingmaterials 40 are allowed to flow into the depressions 36 of the bumps 34so as not to spread to the adjacent pads 12 (bumps 34). In other words,part of the soldering or brazing materials 40 flowing from the bumps 34upon melting is prevented from spreading in the direction parallel tothe surface of the semiconductor chip 10 (lateral direction) and isabsorbed in the direction of the height of the bumps 34 (verticaldirection). This prevents occurrence of a short circuit between each pad12, thereby increasing the yield in the fabrication of the semiconductordevice.

[0160] The soldering or brazing materials 40 may be applied to the bumps34 of the semiconductor chip 10, through which the bumps 34 may bebonded to the interconnect pattern 52 (lands) The soldering or brazingmaterials 40 may be applied to the interconnect pattern 52 (lands) onthe substrate 50. The bumps 34 may be bonded to the interconnect pattern52 (lands) due to surface tension of the soldering or brazing materials40 during melting.

[0161] The leads may be inner leads in the case where the TAB technologyis applied, or all conductive members bonded through the soldering orbrazing materials 40.

[0162] A semiconductor device according to the present embodimentincludes the semiconductor chip 10 including a plurality of pads 12, themetal layers (bumps 34) connected to each pad 12, and a plurality ofleads (interconnect pattern 52). The metal layers have regions intowhich the soldering or brazing materials 40 flow. Each metal layer isbonded to one of the leads through the soldering or brazing materials40. In this case, each metal layer has regions for receiving thesoldering or brazing materials 40. The metal layers may be the abovebumps 34. Part of the soldering or brazing materials 40 flows into thedepressions 36 of the bumps 34. Other structures are the same asdescribed above. The leads may be the interconnect pattern 52 formed onthe substrate 50.

[0163] External terminals 54 connected to the interconnect pattern 52may be formed on the substrate 50. For example, the external terminals54 which are connected to the interconnect pattern 52 throughthrough-holes (not shown) formed in the substrate 50 may be formed. Theexternal terminals 54 may be formed by solder balls. Instead ofpositively forming the external terminals 54, solder cream may beapplied to the interconnect pattern of the circuit board, and thesemiconductor device may be mounted on the circuit board due to surfacetension during melting.

[0164] According to the present embodiment, the soldering or brazingmaterials 40 can be prevented from spreading outside the metal layers byallowing part of the soldering or brazing materials 40 to flow into theregions (depressions 36) of the metal layers (bumps 34). Specifically,the soldering or brazing materials 40 melted on the metal layers can beprevented from flowing onto the adjacent pads 12. Therefore, a highlyreliable semiconductor device can be provided by preventing occurrenceof a short circuit between the pads 12.

[0165] (Second Embodiment)

[0166] FIGS. 8 to 11 are views showing a method for forming bumpsaccording to a second embodiment to which the present invention isapplied. The present embodiment differs from the first embodiment as tothe formation method and the structure of metal layers (bumps 74). Thedescription relating to the first embodiment may be applied to thefollowing embodiment as far as possible.

[0167] A resist layer 60 is formed on the semiconductor chip 10, asshown in FIGS. 8 and 9A. The resist layer 60 has a plurality ofthrough-holes 62, at least part (part or all) of which is superposed onone pad 12. A plurality of through-holes 62 may be disposed inside thepads 12 or located outside of the circumference of the pads 12. Theresist layer 60 is formed while allowing a portion 64 to remain insidethe pads 12 in order to form a plurality of through-holes 62. The shapeof the through-holes 62 may be either rectangular as shown in FIG. 8 orcircular without specific limitations. The portion 64 of the resistlayer 60 is formed to provide a region 76 between metal layers (firstand second metal layers 70 and 72) as described later. The portion 64 isformed to a size so as to allow the soldering or brazing material 40 toflow into the region 76. The arrangement and the number of through-holes62 may be appropriately determined taking into consideration the sizewhich allows the soldering or brazing material 40 to flow into theregion 76.

[0168] Part of the insulating film 14 is removed through a plurality ofthrough-holes 62 in the resist layer 60, as shown in FIG. 9B.Specifically, a plurality of openings 66 is formed in the insulatingfilm 14 on each pad 12 using the through-holes 62. In other words, aplurality of exposed areas is formed on each pad 12. This enables aplurality of bumps to be formed on each pad 12 so as to be connected tothe pads 12 . The size of a plurality of exposed areas in each pad 12 isnot limited. For example, the exposed area may be in the shape of asquare with a side length of about 20 pm.

[0169] First and second metal layers 70 and 72 are formed as shown inFIG. 9C. For example, the first metal layers 70 maybe formed in eachthrough-hole 62. The second metal layers 72 may be formed so as to coverthe surface of the first metal layers 70 after removing the resist layer60. Bumps 74 including the first and second metal layers 70 and 72 areformed in this manner. A plurality of bumps 74 can be formed on each pad12 by forming a plurality of through-holes 62 for each pad 12.

[0170] The region 76 is formed between the adjacent bumps 74 on each pad12, as shown in FIG. 9C. Specifically, the regions 76 between the bumps74 are formed by allowing the portions 64 of the resist layer 60 toremain. In the case of forming the second metal layers 72 after removingthe resist layer 60, it is preferable to form thin second metal layers72 so that the regions 76 are not filled with the second metal layers72.

[0171] The formation method and other structures of the first and secondmetal layers 70 and 72 may be the same as described above. In thepresent embodiment, the first metal layers 70 may be formed so that atleast one depression (see FIG. 5) is formed on the side of the firstmetal layers 70, as illustrated for the above embodiment.

[0172] Brazing materials 80 may be applied to the bumps 74. Thesoldering or brazing materials 80 may be solder as described above.Solder may be applied to each bump 74 by dipping the bumps 74 into asolder bath, for example. The amount of solder applied to the bumps 74can be decreased by forming a plurality of bumps 74 on each pad 12,thereby preventing an excess amount of solder from flowing out.

[0173]FIG. 10 is a lateral cross-sectional view showing the bumps 74(first and second metal layers 70 and 72) parallel to a plan view of thesemiconductor chip 10. The regions 76 formed between the adjacent bumps74 on each pad 12 are of a size so as to allow the soldering or brazingmaterials 80 to flow into the regions 76. The regions 76 may beappropriately determined by the number and arrangement of thethrough-holes 62 formed in the resist layer 60.

[0174] According to the present embodiment, the soldering or brazingmaterials 80 can be prevented from spreading outside the bumps 74 whenallowing the soldering or brazing materials 80 to melt on the bumps 74.Specifically, the regions 76 formed between the adjacent bumps 74 oneach pad 12 absorb part of the soldering or brazing materials 80 flowingoutside the bumps 74 upon melting. Specifically, the melted soldering orbrazing materials 80 can be prevented from spreading in the directionparallel to the surface of the semiconductor chip 10 (lateraldirection), and are absorbed in the direction of the thickness of thebumps 74 (vertical direction).

[0175]FIG. 11 is a view showing a method for forming bumps according toa modification example of the present embodiment. Second metal layers 73may be formed on the upper surface of the first metal layers 70, asshown in FIG. 11. The second metal layers 73 may be formed using aplurality of through-holes 62 in the resist layer 60. Allowing no goldlayer (second metal layer 73) to be formed on the side of the bumps 75more reliably prevents the melted solder from spreading from the side ofthe bumps 75 in the lateral direction.

[0176] (Third Embodiment)

[0177]FIGS. 12A and 12B are views showing a method for forming bumpsaccording to a third embodiment to which the present invention isapplied. The present embodiment differs from the above embodiments as tothe formation method and structure of metal layers (bumps 100).

[0178] A resist layer 90 is formed on the semiconductor chip 10, asshown in FIG. 12A. The resist layer 90 is provided with through-holes92, with at least part (part or all) of each superposed on the pads 12.The through-holes 92 are formed in the resist layer 90 so that part ofthe resist layer 90 remains at the center of the through-holes 92 in aplan view of the semiconductor chip 10. For example, the through-holes92 are formed in the shape of a ring which encloses the center (portion94 of the resist layer 90).

[0179] The through-holes 92 may be formed in the shape of either asquare ring or a circular ring. The portion 94 of the resist layer 90forms a region (depression 102) of bumps 100 (including first and secondmetal layers) formed later. The portion 94 of the resist layer 90 ispreferably formed small enough to allow the bumps 100 to be securelyconnected to the pads 12, but large enough to allow the soldering orbrazing materials to flow into the depressions 102 of the bump 100.

[0180]FIG. 12B is a lateral cross-sectional view showing the bumps 100parallel to a plan view of the semiconductor chip 10. The bumps 100 areformed into the shape of a ring so that the depression 102 is formed atthe center in a plan view of the semiconductor chip 10. The depressions102 are formed in the direction of the height of the bumps 100. Part ofthe pads 12 may be exposed at the bottom of the depressions 102. Theshape of the depressions 102 may be either circular or square. Eitherone or a plurality of depressions 102 may be formed.

[0181] According to the present embodiment, part of the soldering orbrazing materials flowing outside the bumps 100 upon melting can beabsorbed into the depressions 102 of the bumps 100. Specifically, themelted soldering or brazing materials can be absorbed in the directionof the height of the bumps 100 (vertical direction) by preventing thesoldering or brazing materials from spreading in the direction parallelto the surface of the semiconductor chip 10 (lateral direction)Moreover, the melted soldering or brazing materials can be preventedfrom flowing outside in one direction by forming the depressions 102 atthe center of the bumps 100. Specifically, an excess amount of solderingor brazing materials can be absorbed uniformly.

[0182] Any of the above embodiments may be applied to the presentembodiment. Specifically, the bumps 100 may have at least one depressionon the side in the present embodiment. A plurality of bumps 100 may beformed on each pad 12. Bumps may be formed by combining thesestructures.

[0183]FIG. 13 shows a circuit board 200 equipped with a semiconductordevice 1 according to the present embodiment. The circuit board 200 isgenerally formed using an organic substrate such as a glass epoxysubstrate or a polyimide film or a glass substrate such as a liquidcrystal display substrate. An interconnect pattern formed of copper orthe like is formed on the circuit board 200 so as to form a desiredcircuit. The interconnect pattern and the semiconductor device 1 areelectrically connected by mechanically connecting the interconnectpattern with the external terminals 54 of the semiconductor device 1.

[0184]FIGS. 14 and 15 respectively illustrate a notebook-type personalcomputer 300 and a portable telephone 400 as examples of an electronicinstrument equipped with the semiconductor device 1 to which the presentinvention is applied.

What is claimed is:
 1. A method for forming a bump comprising the stepsof: forming a resist layer so that a through-hole formed therein islocated on a pad; and forming a metal layer to be electrically connectedto the pad conforming to the shape of the through-hole, wherein themetal layer is formed so as to have a shape in which is formed a regionfor receiving a soldering or brazing material.
 2. The method for forminga bump according to claim 1, wherein the resist layer is formed so as tohave a projection on the inner side of the through-hole.
 3. The methodfor forming a bump according to claim 1, wherein the resist layer isformed so that part of the resist layer remains at the center of thethrough-hole.
 4. The method for forming a bump according to claim 1,wherein a plurality of the through-holes are formed in the resist layerso that at least a part of each of the through-holes is superposed onthe pad, and a plurality of the metal layers are formed, each of theplurality of the metal layers conforming to each of the through-holes toform the region for receiving the soldering or brazing material betweenthe adjacent metal layers of the plurality of the metal layers on thepad.
 5. The method for forming a bump according to claim 1, wherein themetal layer comprises first and second metal layers, wherein the firstmetal layer is formed in a state in which the resist layer is formed,and the second metal layer is formed on the first metal layer.
 6. Themethod for forming a bump according to claim 1, wherein the metal layercomprises first and second metal layers, wherein the first metal layeris formed in a state in which the resist layer is formed, and afterremoving the resist layer, the second metal layer is formed so as tocover a surface of the first metal layer.
 7. The method for forming abump according to claim 5, wherein the pad is covered with an insulatingfilm, the resist layer is formed on the insulating film, an opening forexposing at least part of the pad is formed in the insulating film afterforming the through-hole in the resist layer, and the first metal layeris formed on the pad in a state in which the resist layer is formed. 8.The method for forming a bump according to claim 6, wherein the pad iscovered with an insulating film, the resist layer is formed on theinsulating film, an opening for exposing at least part of the pad isformed in the insulating film after forming the through-hole in theresist layer, and the first metal layer is formed on the pad in a statein which the resist layer is formed.
 9. The method for forming a bumpaccording to claim 5, wherein the first and second metal layers areformed by electroless plating.
 10. The method for forming a bumpaccording to claim 6, wherein the first and second metal layers areformed by electroless plating.
 11. The method for forming a bumpaccording to claim 5, wherein the first metal layer is formed of amaterial containing nickel.
 12. The method for forming a bump accordingto claim 6, wherein the first metal layer is formed of a materialcontaining nickel.
 13. The method for forming a bump according to claim5, wherein the second metal layer is formed of a material containinggold.
 14. The method for forming a bump according to claim 6, whereinthe second metal layer is formed of a material containing gold.
 15. Amethod of fabricating a semiconductor device comprising the steps of:bonding a plurality of metal layers to a plurality of leads through asoldering or brazing material, each of the metal layers formed on eachof a plurality of pads of a semiconductor chip , each of the metallayers having a shape in which is formed a region for receiving thesoldering or brazing material, wherein the soldering or brazingmaterial, when melted, is allowed to flow into the region of each of themetal layers for receiving the soldering or brazing material so as notto spread onto an adjacent pad of the plurality of pads.
 16. The methodof fabricating a semiconductor device according to claim 15, wherein atleast one depression is formed in a side of one of the metal layers, andthe soldering or brazing material is allowed to flow into thedepression.
 17. The method of fabricating a semiconductor deviceaccording to claim 15, wherein one of the metal layers is formed so thata depression which is provided in the direction of the height of themetal layers is formed at the center, and the soldering or brazingmaterial is allowed to flow into the depression.
 18. The method offabricating a semiconductor device according to claim 15, wherein two ormore metal layers of the plurality of metal layers are formed so as tobe connected to one of the pads, and the soldering or brazing materialis allowed to flow into a region formed between the adjacent metallayers of the plurality of metal layers on one of the pads.
 19. Asemiconductor device fabricated by the fabrication method according toclaim
 15. 20. A semiconductor chip comprising a plurality of pads, and ametal layer disposed on each of the pads which is formed to have a shapein which is formed a region for receiving a soldering or brazingmaterial.
 21. The semiconductor chip according to claim 20, wherein atleast one depression is formed in a side of the metal layer.
 22. Thesemiconductor chip according to claim 20, wherein a depression which isprovided in the direction of the height of the metal layer is formed atthe center of the metal layer.
 23. The semiconductor chip according toclaim 20, wherein two or more the metal layers are formed on one of thepads.
 24. A semiconductor device comprising: a semiconductor chip havinga plurality of pads; a metal layer disposed on each of the pads, themetal layer formed to have a shape in which is formed a region forreceiving a soldering or brazing material; and a plurality of leads,wherein the metal layer is bonded to one of the leads through thesoldering or brazing material, and part of the soldering or brazingmaterial is put in the region for receiving the soldering or brazingmaterial.
 25. The semiconductor device according to claim 24, wherein atleast one depression is formed in a side of the metal layer, and thesoldering or brazing material is put in the depression.
 26. Thesemiconductor device according to claim 24, wherein a depression whichis provided in the direction of the height of the metal layer is formedat the center of the metal layer, and the soldering or brazing materialis put in the depression.
 27. The semiconductor device according toclaim 24, wherein two or more the metal layers are formed on one of thepads, and the soldering or brazing material is put in a region formedbetween adjacent metal layers of the two or more the metal layers on oneof the pads.
 28. A circuit board on which is mounted the semiconductordevice according to claim
 24. 29. An electronic instrument comprisingthe semiconductor device according to claim 24.